This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-260231, filed Aug. 29, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the invention relates to a semiconductor memory assembled in a flip chip package wherein a memory cell array is divided into a plurality of subarrays arranged in matrix form and external connection pads are placed in a middle section of the subarray matrix, and to the arrangement of pads and control signal lines in a memory chip. The flip chip package semiconductor memory is applied to a high-speed SPAM (Static Random Access Memory) and the like.
2. Description of the Related Art
A flip chip package type semiconductor memory is widely used in a high-speed SRAM and the like because the degree of freedom of arrangement of pads on a memory chip is high and thus the pads can be scattered on a memory cell array (or between subarrays).
The pattern layout of a prior art memory chip assembled in a flip chip package will now be described with reference to FIG. 1. The memory chip shown in FIG. 1 includes a memory cell array that is divided into a plurality of subarrays arranged in matrix form. For example, the memory cell array is divided into subarrays SA1,1 to SA16,16 of a matrix with 16 rows and 16 columns. Thus, the j-th subarray column (j is an integer smaller than 17) includes sixteen subarrays SAj,1 to SAj,16. Hereinafter, the column numbers of matrix elements are each represented by a first suffix and the row numbers thereof are each represented by a second suffix.
As shown in FIG. 1, a first peripheral circuit area 11 is formed in a middle section of a subarray matrix, which extends in the row direction, and a second peripheral circuit area 12 is formed in a middle section of the subarray matrix, which extends in the column direction. The first peripheral circuit area 11 supplies a subarray control signal to each of sixteen subarrays SAj,1 to SAj,16 included in the j-th subarray column.
In the prior art memory chip shown in FIG. 1, the first peripheral circuit area 11 is interposed between the eighth and ninth rows of the subarray matrix and includes sense amplifiers. The second peripheral circuit area 12 is interposed between the eighth and ninth columns of the subarray matrix and includes main row decoders.
External connection pads are arranged in a middle section of the subarray matrix, which extends in the row direction. In this prior art memory chip, a first pad area 21 is formed between the fourth and fifth rows of the subarray matrix and a second pad area 22 is formed between the twelfth and thirteenth rows thereof.
Paying attention to the first subarray column as a representative example, the first peripheral circuit area 11 supplies subarray control signals from control signal drivers DRV1 to DRV16 to sixteen subarrays SA1,1 to SA1,16 via subarray control signal lines S1,1 to S1,16, respectively.
Subarray control signal lines S1,1 to S1,4 extend to their respective subarrays SA1,1 to SA1,4, which are located away from the first peripheral circuit area 11, from the first periphery circuit area 11 through the first pad area 21. Subarray control signal lines S1,13 to S1,16 extend to their respective subarrays SA1,13 to SA1,16, which are located away from the first peripheral circuit area 11, from the first periphery circuit area 11 through the second pad area 22.
In the pattern layout of the prior art memory chip, the subarray columns and the pads Pd of the first pad area 21 differ in pitch from each other. A displacement is therefore caused in the row direction between the subarray columns and pads Pd as shown in FIG. 1.
FIG. 2 is an enlarged view showing an example of the pattern layout in a neighborhood of the first pad area 21 shown in FIG. 1. As is apparent from FIG. 2, the pitch of the subarray columns and that of pads Pd of the first pad area 21 are determined independently. For the sake of simplification of layout design, a plurality of subarray control signal lines Sj,1 to Sj,16 are arranged on the j-th subarray column at the same pitches as those of the subarray columns and thus designed hierarchically.
The subarray control signal lines Sj,1 to Sj,16 on the j-th subarray column are arranged at the same pitches as those of the subarray columns, whereas the pads Pd are arranged at pitches different from those of the subarray columns. Therefore, as shown in FIG. 2, the subarray control signal lines Sj,1 to Sj,16 have to turn and detour around the pads Pd in the pad areas 21 and 22.
If some of the subarray control signal lines Sj,1 to Sj,16 are turned and detoured, then they increase in parasitic capacitance and parasitic resistance by the turn and detour thereof. The delay time of control signals of the subarray control signal lines is therefore lengthened more than that of controls signals of the subarray control signal lines that do not turn or detour around the pads. The delay time of the control signals vary with the subarray control signal lines, as does the transmission time of the control signals. It is thus difficult to design a pattern layout of subarray control signal lines in an SRAM that requires a high-speed operation.
If some the subarray control signal lines Sj,1 to Sj,16 are simply displaced without being turned, the pattern layout of subarray control signal lines of each subarray column becomes irregular and thus difficult to design.
As described above, the prior art memory chip having a flip-chip connecting structure has the following problems. When a subarray control signal line is formed between the peripheral circuit area and each of the subarrays, it is turned to make a detour around a corresponding pad in the pad area. The subarray control signals therefore vary in delay time, which makes it difficult to operate the memory chip at high speed.
A semiconductor memory device according to an aspect of the present invention comprises a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns and a plurality of subarray rows, a peripheral circuit area extending in a first direction in a middle section of the memory cell array, a pad area extending in the first direction in a middle section of the memory cell array, which differs from the middle section in which the peripheral circuit area is formed, and a plurality of signal lines each formed in a second direction perpendicular to the first direction so as to connect the peripheral circuit area and a corresponding one of the subarrays of the subarray columns, wherein the pad area includes a plurality of pads arranged in the first direction at pitches corresponding to those of the plurality of subarray columns, and the plurality of signal lines are each formed linearly so as to pass between the pads in the pad area.